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RDS DEMODULATOR + FILTRU

tehnica mecanica







TDA 30B




RDS DEMODULATOR+FILTRU




INALTA PERFORMANTA, FILTRU BANDA57KHz  



ARI (INDICATIE SK) SI IESIRE SEMNAL RDS DE CALITATE

OSCILATOR 4 MHz SAU

MHzOPTIONAL

ZGOMOT REDUSMIXAT BIPOLAR/TEHNOLOGIE CMOS


DESCRIERE

TDA 7330 B este un demodulator RDS care capteaza informatia RDS transmisa de statiile radio FM. Iesirea semnalului de date RDDA si de clock RDCL poate fi procesata de un decodor RDS (microprocessor).

Microprocesorul opereaza conform normelor EBU (EUROPEAN BROADCASTING UNION) si include 2 intrari de filtru de 57kHz, un detector de trecere, un clock, bucla PLL 57kHz, decoder bifazic PSK, decoder diferential, indicator ARI si semnal de iesire RDS de calitate.


DIAGRAMA BLOC







DIP20 SO20

ORDERINGNUMBERS:

TDA7330B TDA 330BD













TDA73 0B



NIVELE MAXIME ABSOLUTE


Simbol

Parametrii

Valoare

Unit

VCC

Alimentare


V

Top

Temperature de operare

-40to85

C

Tstg

Temperatur ambient

-40to150

C




DATE TERMICE


Simbol

Descriere

DIP20

SO20

Unit

Rthj case

Rezistenta termica la scurt circuit Typ.



C/W


PINCONNECTION Topview





DESCRIERE PINI


Nr.

Nume

Descriere

























MUXIN Vref COMP FILOUT GND

T1

T3

T4

OSCOUT OSCIN T57

RDCL RDDA QUAL ARI




VCC

T2

FSEL TM


POR

Intrare RDS. Tensiune de eferinta

Notinvertingcomparatorinput (smoothingfilter) FilterOutput

Ground

Testingoutputpin (nottobeused)

Testingoutputpin (nottobeused) Testingoutputpin(nottobeused) Oscillatoroutput

OscillatorInput

Testingoutputpin:57KHz 16416k104q clockoutput

RDSclockoutput (11 7.5Hz) RDSdataoutput

Outputforsignalqualityindication(High=good)

OutputforARIindication (HighwhenRDS+ARIsignalsarepresent)

(Highwhenonly ARIispresent)

(Lowwhenonly RDSispresent)

(indefinedwhenno signalispresent) SupplyVoltage

Testingoutputpin (nottobeused)

Frequency selectorpin:open=4.332MHz,closedtoVCC =8.664MHz

Testmodepin (open=normalRUN)

closedtoVCC =Testmode) ResetInputfortesting(activehigh)



TDA7 30B



ELECTRICALCHARACTERISTICS(VCC V,Tamb= C;Rg W;fosc= MHz VIN mVrmsunlessotherwisespecified)


Symbol

Parameter

TestCondition

Min.

Typ

Max.

Unit

SUPPLY


VCC

SupplyVoltage




V

IS

SupplyCurrent


mA

RPOR

PORPullDownResistor

pin20


KW

PORON

PORThreshold


V

FILTER measuredanpin4FILOUT


FC

CenterFrequency




KHz 16416k104q

BW

3dBBandwidth




KHz 16416k104q

G

Gain

f=57KHz 16416k104q




dB

A

Attenuation

Df=+4KHz 16416k104q

f=38KHz 16416k104q ; Vi=500mVrms

f=67KHz 16416k104q ; Vi=250mVrms







dB dB dB

DPh

Phasenonlinearity

A(seenote1) B(seenote1) C(seenote1)







DEG DEG DEG

Ri

InputImpedance




KW

S/N

SignaltoNoiseRatio

Vi mVrms



dB

Vi

MaximumInputSignalCapability

f =19KHz 16416k104q ;T3<-40dB(seenote2)

f=57KHz 16416k104q (RDS+ARI)



Vrms mVrms

RL

LoadImpedance

Pin4


KW

CROSS DETECTOR


RA

Resistancepin3-4




KW

OSCILLATOR


FOSC



OscillatorFrequency

FSEL     =Open(*)

FSEL     =ClosedtoVCC



MHz

MHz

VCLL

ClockInputlevelLOW(pin10)


V

VCLH

ClockInputLevelHIGH(pin 0)


V

OutputAmplitude(pin9)


VPP


*)FSEL pinhas an internal KWpulldownresistor A MHz QUARTZmust beused *) A MHz QUARTZmust beused.

DEMODULATOR


DfO

MaxOscillatorDeviation

FSEL     =Open


KHz 16416k104q

SRDS

RDSDetectionSensitivity


mVrms

SARI

ARIDetectionSensitivity


mVrms

Tlock

RDSLockupTime


ms

VOH

OutputHIGHVoltage

IL=0.5mA;pins1 ,13,14,15


V

VOL

OutputLOWVoltage

IL=0.5mA;   pins1 ,13,14,15


V

fRDS

DataRateforRDS

RDCLpin


Hz

tD

RDDATransitionversusRDCL

(seefigure2)


msec


Note(

Thephasenonlinearityis defined as:DPh=|-2 ff ff ff

whereffxistheinput-output phasedifferenceatthefrequencyfx x=




TDA73 0B


ELECTRICALCHARACTERISTICS(continued)


Measure

f1 KHz)

f2 KHz)

f3(KHz)

DPhmax

A




<5

B




<7.5

C




<10


Note( The thharmonic KHz) must be lessthan 40dBinrespectto the inputsignal KHz plus gain.


Figure :RDS timingdiagram






OUTPUT TIMING

The generated 5Hz   output clocRDCL line)issynchronizedtotheincomingdata. According to the internal PLL lock condition this


Figure :TestCircuit

data change can resultson the falling oron the

risingclockedge.

Whicheverclockedgeisusedby thedecoder ris

ingorfalling edge)thedatawillremainvalidfor

msecaftertheclock transition.





TDA7 30B


APLICATII

A gooDdecoupling between VCC   and

GROUND isnecessary: a 100nF ceramicca-

pacitor,withlowresistanceandlowinductance athighfrequency,directlyconnectedonpin

(VCC)and5(GND)isrecommended.

Asmall seriesinductance ( mH) or resistor

W)maybeusedforsupplylinefiltering.

The Layout pathpin2-C2-pin5must beas

shortas possible.

If thesupplyline,afterthepoweronhasasoft and disturbed (spikes) slope, a capacitoof

100nF betweePOR and VCCiracom mended.

Thevarioustestingpinshavenosenseforthe customer

Figure :P C.boardandcomponentlayoutoffig.3 1scale)








TDA73 0B


  Figura Gainvs.FrequencFigura :GroupDelayvs.Frequency




TDA7 30B







DIM


mm


inch


MIN.


TIP.


MAX


MIN.


TIP.


MAX


a1






B










b






b1






D






E






e






e3






F






I






L








Z





 












DIP







IM


mm


inch


MIN.


TIP.


MAX


MIN.


TIP.


MAX


A










A1










B










C










D










E










e






H










h










L










K


min ˚ max.)

  TDA73 0B




DATE MECANICE






SO







L




A





D







E





SO20MEC





TDA7 30B



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